1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a redundancy circuit.
2. Background Art
The shrinkage of unit cells has accelerated with the high density of semiconductor memory devices, thus cutting down on the yield rate for good chips. Therefore, recent semiconductor memory devices usually employ a redundancy circuit with a spare cell for replacing a defective cell. The semiconductor memory device with the redundancy circuit has a normal decoder connected to a normal word line-and a redundant decoder connected to a redundant word line. The normal decoder receives the shaped row address and the redundant decoder senses the state of the memory cell to provide a sense signal indicative of the normal mode or redundancy mode, thereby selecting the normal word line or the redundant word line. An output of the column decoder selectively turns off or on a column select transistor, transmitting the information from a given cell that is driven and selected by the word lines to an input/output gate connected to the cell.
The conventional redundancy circuit of FIG. 1 is disclosed in U.S. Pat. No. 4,780,851, which was granted to Osama Kurakami.
In normal mode operation, the row decoder selects a word line, and the column decoder 19 selects the given bit line pair, accessing the information in the memory cell. The column select transistor is turned on to transfer data from the memory cell of the main memory array to the input/output gate. On the other hand, in redundancy mode operation, an output Yi of the column decoder 19 asserts a logical "high," turning off the column select transistors NP1, NP2, NP3 and NP4. Accordingly, the information of the column with the defective memory cell is not delivered to the input/output gate connected to the column select transistors. That is, access of the column with the defective memory cell is suppressed. Thereafter, the normal cell of the redundancy memory array replaces the defective cell of the main memory array. The information in the accessed normal cell is transferred to the input/output gate performing the data reading and writing operation. If a defective cell of a static random access memory (SRAM) connected to the word line is found, the replacement operation of the redundancy circuit is started.
However, when the defect is detected at point A, B or C, even though the defective memory cell in the main memory array is replaced with the good memory cell in the redundancy memory array, the power consumption caused by the defect at A, B or C is effectively not prevented. Accordingly, programming lines, such as fuses 11 and 12, are disposed at the respective row of the main memory array so that the power voltage V cc is selectively supplied to the memory cell, wherein the redundant memory array is the same structure as shown in FIG. 1. In normal mode, the ground voltage GND or power voltage Vcc is supplied through fuse 11 or 12 of the main memory array, and the fuse of the redundancy memory array is selectively cut according to the respective case. In redundant mode, the voltage supply to the main memory array is blocked by cutting fuse 11 or 12 of the main memory cell array so as to prevent the power consumption caused by the defective cell of the main memory array.
On the other hand, in the case of column replacement, transistors N1 and N2, connected to the bit lines, are turned on by a logical "low" voltage (ground) upon enabling of the chip, and PMOS transistors N3 and N4 (for suppressing the leakage current of the bit lines) are turned on, raising the bit lines to Vcc level. Here, if a current path, which is caused by a defect of the bit line pair during processing, is formed between the bit line and ground voltage, even though the column replacement is carried out, a leakage current through the precharging transistors and clamping transistors is generated from the voltage level to ground level.